
`timescale 1ns / 1ns

module FF_GATE (d,clk,reset,q,qn);
	input	[0:7]	d;
	input			clk,reset;
	output	[0:7]		q;
	output	[0:7]		qn;
reg [0:7] q, qn, rq;



FF_BIT u1 (d[0],clk, reset, q[0], qn[0]); 
FF_BIT u2 (d[1],clk, reset, q[1], qn[1]); 
FF_BIT u3 (d[2],clk, reset, q[2], qn[2]); 
FF_BIT u4 (d[3],clk, reset, q[3], qn[3]); 
FF_BIT u5 (d[4],clk, reset, q[4], qn[4]); 
FF_BIT u6 (d[5],clk, reset, q[5], qn[5]); 
FF_BIT u7 (d[6],clk, reset, q[6], qn[6]); 
FF_BIT u8 (d[7],clk, reset, q[7], qn[7]); 


endmodule



module FF10(d,clk,reset,q, qn);

	input	[0:7]	d;
	input			clk,reset;
	output	[0:7]		q;
	output	[0:7]		qn;
        wire [0:7] d1, d2, d3, d4, d5, d6, d7, d8, d9;
        wire [0:7] qn1, qn2, qn3, qn4, qn5, qn6, qn7, qn8, qn9;

FF_GATE FF_1(d,clk,reset,d1, qn1),
FF_2(d1,clk,reset,d2, qn2),
FF_3(d2,clk,reset,d3, qn3),
FF_4(d3,clk,reset,d4, qn4),
FF_5(d4,clk,reset,d5, qn5),
FF_6(d5,clk,reset,d6, qn6),
FF_7(d6,clk,reset,d7, qn7),
FF_8(d7,clk,reset,d8, qn8),
FF_9(d8,clk,reset,d9, qn9),
FF_10(d9,clk,reset,q, qn);

endmodule



module FF100(d,clk,reset,q, qn);

	input	[0:7]	d;
	input			clk,reset;
	output	[0:7]		q;
	output	[0:7]		qn;

        wire [0:7] xin;
        wire [0:7] d1, d2, d3, d4, d5, d6, d7, d8, d9;
        wire [0:7] qn1, qn2, qn3, qn4, qn5, qn6, qn7, qn8, qn9;

 xnor u[0:7]  (xin, d, d7);


FF10 FLOP10_1(xin,clk,reset,d1, qn1),
FF10_2 (d1,clk,reset,d2, qn2),
FF10_3 (d2,clk,reset,d3, qn3),
FF10_4 (d3,clk,reset,d4, qn4),
FF10_5 (d4,clk,reset,d5, qn5),
FF10_6 (d5,clk,reset,d6, qn6),
FF10_7 (d6,clk,reset,d7, qn7),
FF10_8(d7,clk,reset,d8, qn8),
FF10_9(d8,clk,reset,d9, qn9),
FF10_10(d9,clk,reset, q, qn);

endmodule


module FF1000(d,clk,reset,q, qn);

	input	[0:7]	d;
	input			clk,reset;
	output	[0:7]		q;
	output	[0:7]		qn;

        wire [0:7] d1, d2, d3, d4, d5, d6, d7, d8, d9;
        wire [0:7] qn1, qn2, qn3, qn4, qn5, qn6, qn7, qn8, qn9;
FF100 FLOP100_1(d,clk,reset,d1, qn1),
FF100_2(d1,clk,reset,d2, qn2),
FF100_3(d2,clk,reset,d3, qn3),
FF100_4(d3,clk,reset,d4, qn4),
FF100_5(d4,clk,reset,d5, qn5),
FF100_6(d5,clk,reset,d6, qn6),
FF100_7(d6,clk,reset,d7, qn7),
FF100_8(d7,clk,reset,d8, qn8),
FF100_9(d8,clk,reset,d9, qn9),
FF100_10(d9,clk,reset,q, qn);


endmodule




module FF10000(d,clk,reset,q, qn);

	input	[0:7]	d;
	input			clk,reset;
	output	[0:7]		q;
	output	[0:7]		qn;

        wire [0:7] d1, d2, d3, d4, d5, d6, d7, d8, d9;
        wire [0:7] qn1, qn2, qn3, qn4, qn5, qn6, qn7, qn8, qn9;

FF1000 FLOP1000_1(d,clk,reset,d1, qn1),
FF1000_2(d1,clk,reset,d2, qn2),
FF1000_3(d2,clk,reset,d3, qn3),
FF1000_4(d3,clk,reset,d4, qn4),
FF1000_5(d4,clk,reset,d5, qn5),
FF1000_6(d5,clk,reset,d6, qn6),
FF1000_7(d6,clk,reset,d7, qn7),
FF1000_8(d7,clk,reset,d8, qn8),
FF1000_9(d8,clk,reset,d9, qn9),
FF1000_10(d9,clk,reset,q, qn);


endmodule



module FF100000(d, clk,reset, q, qn);

	input	[0:7]	d;
	input			clk,reset;
	output	[0:7]		q;
	output	[0:7]		qn;

        wire [0:7] d1, d2, d3, d4, d5, d6, d7, d8, d9;
        wire [0:7] qn1, qn2, qn3, qn4, qn5, qn6, qn7, qn8, qn9;


	FF10000 i1(d, clk,reset, d1, qn1);
	FF10000 i2(d1, clk,reset, d2, qn2);
	FF10000 i3(d2, clk,reset, d3, qn3);
	FF10000 i4(d3, clk,reset, d4, qn4);
	FF10000 i5(d4, clk,reset, d5, qn5);
	FF10000 i6(d5, clk,reset, d6, qn6);
	FF10000 i7(d6, clk,reset, d7, qn7);
	FF10000 i8(d7, clk,reset, d8, qn8);
	FF10000 i9(d8, clk,reset, d9, qn9);
	FF10000 i10(d9, clk,reset, q, qn);
endmodule

module FF1000000(d, clk,reset, q, qn);

	input	[0:7]	d;
	input			clk,reset;
	output	[0:7]		q;
	output	[0:7]		qn;

        wire [0:7] d1, d2, d3, d4, d5, d6, d7, d8, d9;
        wire [0:7] qn1, qn2, qn3, qn4, qn5, qn6, qn7, qn8, qn9;

	FF100000 i1(d, clk,reset, d1, qn1);
	FF100000 i2(d1, clk,reset, d2, qn2);
	FF100000 i3(d2, clk,reset, d3, qn3);
	FF100000 i4(d3, clk,reset, d4, qn4);
	FF100000 i5(d4, clk,reset, d5, qn5);
	FF100000 i6(d5, clk,reset, d6, qn6);
	FF100000 i7(d6, clk,reset, d7, qn7);
	FF100000 i8(d7, clk,reset, d8, qn8);
	FF100000 i9(d8, clk,reset, d9, qn9);
	FF100000 i10(d9, clk,reset, q, qn);
endmodule // FF1000000

module FF10000000(d, clk,reset, q, qn);

	input	[0:7]	d;
	input			clk,reset;
	output	[0:7]		q;
	output	[0:7]		qn;

        wire [0:7] d1, d2, d3, d4, d5, d6, d7, d8, d9;
        wire [0:7] qn1, qn2, qn3, qn4, qn5, qn6, qn7, qn8, qn9;

	FF1000000 i1(d, clk,reset, d1, qn1);
	FF1000000 i2(d1, clk,reset, d2, qn2);
	FF1000000 i3(d2, clk,reset, d3, qn3);
	FF1000000 i4(d3, clk,reset, d4, qn4);
	FF1000000 i5(d4, clk,reset, d5, qn5);
	FF1000000 i6(d5, clk,reset, d6, qn6);
	FF1000000 i7(d6, clk,reset, d7, qn7);
	FF1000000 i8(d7, clk,reset, d8, qn8);
	FF1000000 i9(d8, clk,reset, d9, qn9);
	FF1000000 i10(d9, clk,reset, q, qn);
endmodule // FF10000000

